If it is expressed as the multiplication of sum, the same number of gates as in fig.15-14 are used, but the number of AND gate and that of OR gate is switched.įig.
ADDER SUBTRACTOR CIRCUIT DIAGRAM FULL
Other compositions for full adder can be developed. This is made by using the Boole function expression below. The logic diagram of full adder in the sum of multiplication is in fig.15-14. The output C is simplified and earned the expression of 6 characters. In case of the output S, the quadrangles expressed as 1 cannot be combined to the adjacent quadrangles so they cannot be simplified. The 1 in the quadrangle of each map can be earned directly from the truth table. The two maps in fig.15-13 are used to simplify two output functions. Each map is composed of 8 quadrangles since the output is the function of three input variables. To simplify each Boole function, a map is needed for each case. In the input/output logical relationship of full adder circuit, one Boole function corresponds to each output variable so it can be expressed as two Boole functions. It is important to recognize that the bits used in this circuit can be interpreted differently like this. On the other hand, in case of expressing as truth table or composing a circuit as a logical gate, the same binary value in the previous sentence can be considered the variable of Boole function. The truth table of full adder is as fig.15-12. By calculating the sum of three bits, the previous digits becomes the output carry C and the next digit is expressed as S. Among two outputs, the sum is expressed as S and the carry as C. When three bits are added, the sum can become from 0 to 3, and since 2 digits are required to express 2 and 3 as binary numbers so two outputs are needed. The input variables expressed as x and y are two bits of current position that will be added, and the third input variable expressed as Z is the carry from the previous position. It is composed of three inputs and two outputs. Full Adderįull adder is a combination circuit that calculates the sum of three input bits. The half adder can be realized as Exclusive-OR gate and AND gate as in (e). In (d), if C is expressed as the multiplication of sum, it is as below. The complement of S is the equivalence of x and y. (c) is earned from the truth that S is Exclusive-OR of x and y. Based on this, we can see that there are various choices even when making a simple combination logic function like this.įig.15-11(a) is the implementation of half adder in the sum of multiplication, and (b) is that in the multiplication of sum. These all output same result concerning the operation of input and output. The logical expression of this is fig.15-11 and 4 other logical expressions of half adder are in fig.15-11.
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